How to generate the testbench for signal process algorithim?

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fangll

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I want to generate plenty of data as stimulation to simulate the digital receiver design usued verilog. how to generate the modulation data. I know the matlab can do it, but the data file pre-generate can not used for long time simulation because of i need read a very large data file into the testbench routine.
Any one can give me some advice?
thx!
 

Useing simple channel model and write verilog code for it, also write a transmitter verilog model.
 

thank juripero, thank for your help. But if i want to add channel model, such as fade, interference, how can i deal with it. The In-build function in verilog simulation is too little.
 

You are right, Verilog is not so convienient in terms of channel modeling and system simulation, that is why Simulink and Systemview are nomally used for that purpose.
 

Systemview have large channel model lib + related comm sig generators. Can see time/spectrum/BER displays easy.
 

In same case we usualy tes model in C or Systemview and generate files or in best case use real record of input signal. For functional testing you may scale sample ratio (decrease it) and test in generated files
 

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