how to generate jittered signal source?

[beabroad]

jittered signal

HI all

I am now designing a CDR circuit, and want to generate a jittered signal source in Verilog-A to test the function of CDR.
How to do this?
thanks.

 

[skal81]

You can find a Verilog model of a clock with jitter at https://www.designers-guide.org/VerilogAMS/, in the Functional model section. You have the two kinds of jitters modeled. Hope it correpond to what you're looking for.

 

[beabroad]

the data generator in that section is only without jitter. However, i think we can use the Fixed-frequency oscillators with jitter combined with DFF to generate the jittered data source.
or we can just use some of the code in the jittered frequecy oscillator into the data generator to generate the jittered data source