How to generate DVI clock ranging from 52 to 165 MHz?

[hanstarro]

Hi!

I am starting a DVI Board design. The purpose is to generate DVI data in an FPGA. interface it to an DVI transmitter from silicon image. There are quite a lot of data formats to support with dvi. a list is shown below. my question is ho to generate this pixel clocks, ranging from 52MHz to 165MHz. Can anyone give a hint?

we are using a V5LXT with integrated PLL features.


regards
hans


formatver hor FrRatePclk[MHz] Drate [Mbps]
WUXGA 1920 1200 85 281,25 6750
WUXGA 1920 1200 75 245,25 5886
WUXGA 1920 1200 60 193,25 4638
WUXGA 1920 1200 50 158,25 3798
UXGA 1600 1200 85 235 5640
UXGA 1600 1200 75 204,75 4914
UXGA 1600 1200 60 161 3864
UXGA 1600 1200 50 131,5 3156
SXGA 1280 1024 85 159,5 3828
SXGA 1280 1024 75 138,75 3330
SXGA 1280 1024 60 109 2616
SXGA 1280 1024 50 88,5 2124
XGA 1024 768 85 94,5 2268
XGA 1024 768 75 82 1968
XGA 1024 768 60 63,5 1524
XGA 1024 768 50 52 1248

 

[Iouri]

DVI clock generation

I belive V5 has reprogramble PLL, so you can change PLL setting without re-loading FPGA image. check the data sheet. PLlease also note for some high resolution stuff you migh need to DDR access, pay attention when you do layout


Good lack!