It is generated from schematic.Snez said:1) I dont really understand the dsn file. How is it generated?
I can't understand what you mean.Snez said:I see it contains the variables I want to change, but to be able to create it
I can't understand what you mean.Snez said:i need to know what do the many numbers before the circuit specs represent and how are they generated.
% hpeesofsim [-r output_rawfile_name] [netlist_inputfile_name]Snez said:2) What should I call to run the simulation? For momentum it's MomEngine but what is for Transient and or S-param simulation from schematics?
fname = strcat(work_dir, '\networks\circuit.ael');
f = fopen(fname, 'w');
if (f < 0),
error(sprintf('Unable to open output file %s.', fname));
end
fprintf(f, strcat(...
'user = %s\n',...
'set_simulator_type(1);\n',...
'create_item("circuit","circuit","X",16,-1,NULL,"Component Parameters",NULL,"%43?global %;%d:%t %# %44?0%:%31?%C%:_net%c%;%;%e %b%r%8?%29?%:%30?%p %:%k%?[%1i]%;=%p %;%;%;%e%e","circuit","%t%b%r%38?%:\n%39?all_parm%A%:%30?%s%:%k%?[%1i]%;=%s%;%;%;%e%e%;","SYM_0Port",3,NULL,0);\n',...
'set_design_type(1);\n',...
'library_group("*", "*", 1, "circuit");\n'),...
strcat(p, '/', work_dir));
fclose(f);
No.Snez said:@pancho_hideboo: I thought abt the netlists but it doesnt contain all the info I need for the circuit.
I don't think so.Snez said:I looked at the ael file and that seems rather easy to generate from matlab.
Output file is "*.ds" not "citi", although we can output as "citi".Snez said:So create the dsn file, the ael file, cfg file and then the citi file which should be the output of the simulation.
It can't be. If so, simulation can't be run.Snez said:I looked at the netlist but it doesnt seem complete to me.
Like it doesnt have the transmission lines from my subcircuit nor the MESFETM1 model definition
and parameters (from which i need to vary some) nor the substrate info.
the circuit netlist is missing the P1_Tone port and maybe sth else as well.
Also it doesnt contain the info for simulation.
Design Name: circuit
Date: February 22, 2010 11:42:10
ERROR! Port S1 and port S2 in the design ATF55143 are shorted together.
WARNING! Instance PORT1 of type P_1Tone does not have a netlisting definition.
Netlisting finished at 11:42:10
* Design Name: circuit
* Date: February 22, 2010 11:42:10
.subckt ATF55143 G S1 D S2
.param K=5
.param Z1=30
.param Z2=85
CC1 G S1 C=0.143pF
CC2 D S1 C=0.115pF
JFET1 _net403 _net413 _net409 MESFETM1
LL1 G _net413 0.621nH
LL4 S1 _net409 0.238nH
LL6 _net409 S1 0.205nH
LL7 _net403 D 0.778nH
.ends ATF55143
.subckt circuit
.param Pavg=10
.param Rfeed=5100
CC1 0 _net94 C=10000pF
CC2 0 _net123 C=8.2pF
CC3 0 _net93 C=10000pF
CC4 0 _net88 C=8.2pF
CC5 vlow vin C=5.6pF
CC6 Vout _net121 C=2.2pF
LL1 _net121 _net123 10nH
LL2 _net106 _net121 5.6nH
LL3 vlow _net88 2.7nH
RR1 _net123 _net94 18
RR2 vhigh _net106 15
RR3 _net92 _net123 'Rfeed*1'
RR4 0 _net92 910
RR5 _net93 _net92 10
RR6 _net88 _net93 50
VSRC1 _net94 0 3
RTerm2 Vout 0 50
xX1 vlow 0 vhigh 0 ATF55143
.ends circuit
.end
I think very so.Snez said:but Im rather new in ADS
* Design Name: circuit
* Date: February 22, 2010 11:42:10
.subckt ATF55143 G S1 D S2
.param K=5
.param Z1=30
.param Z2=85
CC1 G S1 C=0.143pF
CC2 D S1 C=0.115pF
JFET1 _net403 _net413 _net409 MESFETM1
LL1 G _net413 0.621nH
LL4 S1 _net409 0.238nH
LL6 _net409 S1 0.205nH
LL7 _net403 D 0.778nH
.ends ATF55143
.subckt circuit
.param Pavg=10
.param Rfeed=5100
CC1 0 _net94 C=10000pF
CC2 0 _net123 C=8.2pF
CC3 0 _net93 C=10000pF
CC4 0 _net88 C=8.2pF
CC5 vlow vin C=5.6pF
CC6 Vout _net121 C=2.2pF
LL1 _net121 _net123 10nH
LL2 _net106 _net121 5.6nH
LL3 vlow _net88 2.7nH
RR1 _net123 _net94 18
RR2 vhigh _net106 15
RR3 _net92 _net123 'Rfeed*1'
RR4 0 _net92 910
RR5 _net93 _net92 10
RR6 _net88 _net93 50
VSRC1 _net94 0 3
RTerm2 Vout 0 50
xX1 vlow 0 vhigh 0 ATF55143
.ends circuit
Netlist Translator (*) 330.200 Nov 3 2007
ADS Netlist translation log
Input format: HSPICE
Input filename: C:\users\trial_prj\netlist.cnex
Output format: ADS Netlist file
Output filename: C:\Documents\atf55143.net
Special options:
Processing first line as comment.
Begin translation at Mon Feb 22 12:34:36 2010
Creating netlist.
Reading item definition file "C:\ADS2008/config\spctoiff.cfg"
WARNING: Model "mesfetm1" for device "jfet1" in circuit "atf55143" not found.
Subcircuits found in Spice Netlist: 2
Subcircuits written to ADS Netlist: 2
Translation completed at Mon Feb 22 12:34:36 2010.
; Translated with ADS Netlist Translator (*) 330.200 Nov 3 2007
; Design Name: circuit
; Date: February 22, 2010 12:28:10
define atf55143 ( g s1 d s2)
k=5
z1=30
z2=85
C:cc1 g s1 C=0.143p
C:cc2 d s1 C=0.115p
mesfetm1:jfet1 _net403 _net413 _net409 Mode=1
L:ll1 g _net413 L=0.621n
L:ll4 s1 _net409 L=0.238n
L:ll6 _net409 s1 L=0.205n
L:ll7 _net403 d L=0.778n
end atf55143
define circuit ()
pavg=10
rfeed=5100
C:cc1 0 _net94 C=10000p
C:cc2 0 _net123 C=8.2p
C:cc3 0 _net93 C=10000p
C:cc4 0 _net88 C=8.2p
C:cc5 vlow vin C=5.6p
C:cc6 vout _net121 C=2.2p
L:ll1 _net121 _net123 L=10n
L:ll2 _net106 _net121 L=5.6n
L:ll3 vlow _net88 L=2.7n
R:rr1 _net123 _net94 R=18
R:rr2 vhigh _net106 R=15
R:rr3 _net92 _net123 R=rfeed*1
R:rr4 0 _net92 R=910
R:rr5 _net93 _net92 R=10
R:rr6 _net88 _net93 R=50
V_Source:vsrc1 _net94 0 Vdc=3
R:rterm2 vout 0 R=50
atf55143:xx1 vlow 0 vhigh 0
end circuit
If you use ADS correctly, transmission lines and the model definition are included naturally.Snez said:Do you have an idea why it doesnt include the transmission lines and the model definition?
I can't understand what you want to do.happy.guy2010 said:I don't know how to generate for example a text file from this file for exporting s parameters from the command window.(I am using windows command prompt)
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