How to generate a pulse from one clock domain to another clock domain?

[sitesh]

I want to know about how to write verilog code to generate a pulse from one clock domain to another clock domain.
1. First is operating at 50MHZ frequency.
2. Second is operating at 100MHZ frequency.

 

[saadbinshafique]

Please clarify your question. Do you want to generate 100MHz clock from 50MHz System clock?