how to force the syntheziser to keep a signal

[Al Farouk]

I wrot a VHDL design and I need to delay a signal for certain number of clocks, I write code for the shift register and I used its output. when I synthesuzed it I get a warining that the signal (declar the shift register) is not used and optimized. How can I force the synthesizer to keep this signal as it is.

 

[r_e_m_y]

Hi,

I'm surpised. If you are using the last bit of your shift register as an output, the synthesizer may keep the shift register.
Check your signal names. be sure to use a signal as an output of your design.

 

[RegUser_2]

Typical examples of a shift register description in VHDL and Verilog:

-- 4-bit serial-in and serial-out shift register
-- CLK: in STD_LOGIC;
-- DIN: in STD_LOGIC;
-- DOUT: out STD_LOGIC;

signal REG: STD_LOGIC_VECTOR(3 downto 0);
begin
process (CLK)
begin
if CLK'event and CLK='1' then
REG <= DIN & REG(3 downto 1);
end if;
end process;
DOUT <= REG(0);

// 4-bit serial-in and serial-out shift register

module shift_reg (DOUT, DIN, CLK);
output DOUT;
input DIN, CLK;
reg DOUT;
reg [3:0] REG;

always @(posedge CLK) begin
REG = {DIN, REG[3:1]};
DOUT = REG[0];
end
endmodule

//Example of four-bit shift register
module Shift_reg_01 (Data_in, Data_out, clock, reset);
input Data_in, clock, reset;
output Data_out;
reg [3:0] Data_reg;

assign Data_out = Data_reg[0];

always @ (negedge reset or posedge clock)
begin
if (reset == 1'b0) Data_reg <= 4'b0;
else Data_reg <= {Data_in, Data_reg[3:1]};
end
endmodule

// Example of shift register with "new_signal" formed inside synchronized block
module shift_reg_02 (Data_in, clock, reset, sig_d, new_signal);
input Data_in, clock, reset;
output sig_d, new_signal;
reg sig_a, sig_b, sig_c, sig_d, new_signal;

always @ (posedge reset or posedge clock)
begin
if (reset == 1'b1)
begin
sig_a <= 0;
sig_b <= 0;
sig_c <= 0;
sig_d <= 0;
new_signal <= 1'b0;
end
else
begin
sig_a <= Data_in;
sig_b <= sig_a;
sig_c <= sig_b;
sig_d <= sig_c;
new_signal <= (~ sig_a) & sig_b;
end
end
endmodule

// Example of shift register with "new_signal" formed outside synchronized block as a continuous assignment.
module shift_reg_03 (Data_in, clock, reset, sig_d, new_signal);
input Data_in, clock, reset;
output sig_d, new_signal;
reg sig_a, sig_b, sig_c, sig_d;

always @ (posedge reset or posedge clock) begin
if (reset ==1'b1)
begin
sig_a <= 1'b0;
sig_b <= 1'b0;
sig_c <= 1'b0;
sig_d <= 1'b0;
end
else
begin
sig_a <= Data_in;
sig_b <= sig_a;
sig_c <= sig_b;
sig_d <= sig_c;
end
end

assign new_signal = (~sig_a) & sig_b;
endmodule

 

[karlheinz]

Wich syntheziser do you use ?

 

[Al Farouk]

I use Le@n@rdo v2001_1a.32

By the way I use each stage of the shift register by oerforming OR operation between them and despite that the warning say that the signal (shift register) not used optimized.

 

[cfft]

If you use synplifypro,it's very easy to do it from the help of synplify.

 

[zape]

Send your code. It shall be easier to check.