how to fix time violation during synthesis a scenario

Hi I have a path in tming report that is giving me setup violation after synthesis , I tried to fix it by giving it more weight in design compiler but still it is not meeting what is the next step i can do . it is violating with 300ps and if ican mange it to 100ps it is ok for me to go as client has given me this margin .

Thanks

RTL coding modifications.
Synthesis of this sub-block before doing the whole system.
Force the tool to use the force speed grade (rc for example: set_attribute user_speed_grade very_fast [get_attribute subdesign ...])

rca said:

RTL coding modifications.
Synthesis of this sub-block before doing the whole system.
Force the tool to use the force speed grade (rc for example: set_attribute user_speed_grade very_fast [get_attribute subdesign ...])

Click to expand...

thanks rca ..

Try to enable "boundary optimization" during synthesis and see the result. If boundary optimization is enabled combo path across module boundaries will get optimized.

You can also try cell sizing for the cells in the critical path. Use bigger cells instead of existing cells.

sharath666 said:

You can also try cell sizing for the cells in the critical path. Use bigger cells instead of existing cells.

Click to expand...

these all the stpes i tried let say everything is is at it's optimum level then what you will do??? and remember it is at synthesis level.

my personal opinion - before trying / adding anything to the existing vanilla script that your using is to debug.
I would review the timing report to see if what causes this violation to occur
- is it the cell delays impacting the timing thereby cell selection during synthesis
- has synthesis not optimized the netlist
- has it not done better opto, is there room to optimize logic to reduce level of hierarchy
- are there any preserves
- constraints are well applied - is it a multicycle , delays, pessimism etc

depending on what you diagnose is something that i would add in the scripts else its all trial and error and machine time while we wait for results.

Say you see that it traverses across hierarchies - i would try ungroup, say cell delays are high or it has not used complex cells - i would review the dont_use list etc and so on