How to fix FPGA timing violation in Altera Maxplus2?

[no_mad]

timing violation in FPGA

Hi

I'm using Altera Maxplus2 software for my fpga design. During the simulation, there are timing violations. I'm not very familiar with fpga based design, I'm use to Synopsys Design Compiler, which is an ASIC.

Thus, in fpga how do u fix these timing violations??

Please enlighten me....

thanx in advance,
-no_mad

 

[tut]

timing violation in FPGA

**broken link removed**

 

[no_mad]

timing violation in FPGA

Hi tut,

This weblink doesnt give enough info on how to solve the setup time. It only determine the cause of the setup or hold time violation.

I already know the source of my timing violation. I would highly appreciate if u can tell me how to fix the setup and hold time.

In asic, to fix hold time we can do it during the synthesis. Ex DC shell...with "set_fix_hold" command.

Now, I have no idea on how to fix it in FPGA.

 

[tut]

timing violation in FPGA

Setup time violations are corrected in two ways.
First, extra buffers can be inserted to speed up slow signals.
Second, if buffer insertion does not completely fix the setup violation, the
placement can be re-optimized.

Hold-time violations are fixed by inserting delay elements into fast data paths.

Excerpt from
https://www.altera.com/literature/hb/hrd/hc_h51019.pdf

Try revising your constraints, retiming is also an option..
If u r observing skew, try compensating it by adding dummy logic in the data path
to delay it..
Reducing number of logic levels can also help..

 

[no_mad]

timing violation in FPGA

Thanx a lot tut. I really appreciate it.

I will try revising my constraints.