ryan1122
Newbie
Hi, I am new to verilog-hdl design. I am using xilinx vivado in order to synthesize and implement the design. The design basically a FFT algorithm. I want to calculate the percentage of "Fully used LUT-FF pairs" used by the design. After implementation by selecting a FPGA device the total Fully used LUT-FF pairs consumed is come out as 162. I have attached the report. But, I did not find the total no. of available Fully used LUT-FF pairs. From the report can I find the total no. of Fully used LUT-FF pairs present in that FPGA device or where could I find it??