I don't see anything "wrong" with your simulation. A few observations:
1. In the case where the load resistance is very high (near infinity), the only source of loss is due to the FET's Coss charging and discharging. The LTspice model takes about 40nC of charge to change Vds from 0V to 600V. The energy required is that multiplied by the bus voltage, which is 40nC*600V=24uJ. This happens twice per switching period (once for each edge), and for each half bridge, so combined switching loss across all four FETs is 96uJ*Fsw.
2. When the load resistance is lower (like 100-1K), then things get more complicated. As load current increases, overlap switching losses will increase. Overlap switching losses will also depend on switching time, but because your gate drive is so fast it's still very low. Capacitive switching losses on the other hand actually decreases due to the load resistance. This is because much of the energy stored in the capacitances will now be delivered to the load instead of dissipated in the FETs. Overall, you may paradoxically observe that total switching losses is much lower than with no load at all.
3. If you keep reducing Rload, eventually overlap switching losses will start contributing significantly, but by then the total losses will be so high that the device will be dead anyways.
But if your intent is to work on a LLC design, I don't understand what the purpose of this simulation with a simple load resistance actually is. It's not going to be directly comparable to an LLC circuit.
When operating properly (i.e., all FETs turn on with near zero voltage), it is expected that switching loss will be nearly zero, and therefore switching frequency will have no direct impact on efficiency (assuming that as frequency is changed the design of the LLC network also changes to maintain constant output power). That's the main point of the LLC topology.
Maybe state some more specific questions then...