FlyingDutch
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Hello,
in my last design in FPGA I encountered difficulties with differential clock pins. My FPGA board is:
https://pl.aliexpress.com/item/32959887279.html?spm=a2g17.12010612.8148356.4.1a4954bdnHb81i
with Spartan7 IC - exactly XC7S15-FTGB196
In Vivado project I made block design of Microblaze MCU. This block has input of differential clock (100MHz) as it's input port. On My FPGA board I have single clock of frequency 50 MHz..
In order to provide such clock to MCU desing I used clok wizard IP where i generated 100 Mhz single clock. Then I input this clock to OBUFDS primitive and from it's outputs go out two pins of differential clock (n and p).
My question is how to find for this Spartan7 chip and map in constraint file suitable pins for such clock.
I am showing a part of VHDL code with clock wizard and OBUFDS buffer:
i am also not sure if IOSTANDARD=>"DEFAULT" is OK, or should I explicite give one of differential standars (for example DIFF_HSTL_II_18).
Could I ask for help with this question?
Best Regards
in my last design in FPGA I encountered difficulties with differential clock pins. My FPGA board is:
https://pl.aliexpress.com/item/32959887279.html?spm=a2g17.12010612.8148356.4.1a4954bdnHb81i
with Spartan7 IC - exactly XC7S15-FTGB196
In Vivado project I made block design of Microblaze MCU. This block has input of differential clock (100MHz) as it's input port. On My FPGA board I have single clock of frequency 50 MHz..
In order to provide such clock to MCU desing I used clok wizard IP where i generated 100 Mhz single clock. Then I input this clock to OBUFDS primitive and from it's outputs go out two pins of differential clock (n and p).
My question is how to find for this Spartan7 chip and map in constraint file suitable pins for such clock.
I am showing a part of VHDL code with clock wizard and OBUFDS buffer:
Code:
PLL: clk_wiz_0 port map (clk50MHz,reset_rtl_0, clk100MHz);
--Output buffer for diff clock (out)
OBUFDS_buffer : OBUFDS
generic map(
IOSTANDARD=>"DEFAULT", --SpecifytheoutputI/Ostandard
SLEW=>"SLOW") --Specifytheoutputslewrate
port map(
O => Odiff_clock_rtl_0_clk_p, --Diff_poutput(connectdirectlytotop-levelport)
OB => Odiff_clock_rtl_0_clk_n, --Diff_noutput(connectdirectlytotop-levelport)
I => clk100MHz --Bufferinput
);i am also not sure if IOSTANDARD=>"DEFAULT" is OK, or should I explicite give one of differential standars (for example DIFF_HSTL_II_18).
Could I ask for help with this question?
Best Regards