how to find path to set_disable_timing?

[Jordon]

hi, i am synthesis a dsp module from eFPGA. And as a simliar architecture compared with FPGA, there some combinational loops in this module, so i want to break them.
I found some detailed description in a paper: https://dl.acm.org/doi/10.1145/3024063 . And it described at page 10 as:

Design Compiler accepts area and timing constraints, permitting one to trade off performance versus area for a single RTL design by changing constraints. In our experimental study (Section 5), we synthesize area-optimized, timing-optimized, and balanced FPGAs. Optimizing for area is straightforward: we direct Design Compiler to achieve a target area of zero. Optimizing for timing is more involved, owing to the fact that FPGAs contain many combinational loops before being programmed. In other words, the ASIC tools are synthesizing an unconfigured FPGA and “see” many paths from a cell output, through routing, and back again to the same cell—combinational loops that are not present when the FPGA is configured for a practical/real application. Such loops are problematic for timing analysis, and they must be “broken” prior to timing-constrained synthesis. The loops exist within both inter- and intra-logic block routing, and combinations of these. Figure 6 show examples of combinational loops and how we break such loops (via automatically generated constraints provided to Synopsys). It is clear that inter-logic block routing will contain many of these loops, and to ensure that all loops are broken, all of the MUXes in the top level will be disabled during top-level timing analysis. This means that when compiling the MUXes, timing constraints are still applied. Within a logic block, there are various places the loop can be broken. We decided to break the loop at the output MUX, which selects between the combinational or registered path. This choice ensures that paths through the FF will be timing optimized. The loops are broken using the set_disable_timing constraint. In essence, after breaking such loops and by using the bottom-up synthesis approach, we are able to produce a timing-optimized implementation of each module; however, all possible timing paths through the overall FPGA (i.e., across modules) are not optimized globally.

That must be a stupid question, but i tried some ways to set_disable_timing, not works. I mean, although i know how the `set_disable_timing` script defined, like:

set_disable_timing [get_pins my_lib/XX]

I could not find where the object `pin` comes from, A RTL codes? netlist? or some other location...
Take a example, in this paper, I want to `set_disable_timing` in MUX output, how can i find the script's objection pins, from netlist? RTL codes, or those information in DC synthesis log？

 

[ThisIsNotSam]

set_disable_timing can be applied to a lib cell or to a specific instance of the netlist.
you can do something like set_disable_timing mylib/mymux/S to stop the tool from doing any timing calculation related to the S pin of all muxes i nthe design. this is likely too aggressive and not what you want

you can do set_disable_timing on the hierarchy as well. set_disable_timing mytop/mymodule/data_in would be an example. this is likely what you need.

you can achieve the same with false_paths if you find that more intuitive

 

[Qwerty112233]

I used
check_design -type loops -verbose

To give me the loop. Then you inspect it yourself or get with designer to root cause it. If it's a rtl problem then rtl can fix it. If it's something that needs to be handled in PD, use set disable timing -from cell/pina -to cell/pinZ

 

[ThisIsNotSam]

I used
check_design -type loops -verbose

To give me the loop. Then you inspect it yourself or get with designer to root cause it. If it's a rtl problem then rtl can fix it. If it's something that needs to be handled in PD, use set disable timing -from cell/pina -to cell/pinZ

the design itself has loops because it is an eFPGA. cannot be fixed in RTL.

 

[Qwerty112233]

the design itself has loops because it is an eFPGA. cannot be fixed in RTL.

"If it's something that needs to be handled in PD, use
set disable timing -from cell/pina -to cell/pinZ "