As TrickyDicky has said, you have to look at the compilation reports. If this code is intended for an FPGA, you have to build the coding using the vendor-specific tool chain, and the compilation report will tell you the amount of resources (i.e. LUTs, RAMs, etc) used by our code.
If the code is intended for an ASIC, then use Synopsys Design Compiler or similar, with the vendor libraries, and the compilation report will have the combinatorial and sequential gate counts, memory usage etc.
Without knowing which design technology is the target of your code, we can't be more specific.
r.b.