lannister7
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May i ask you to pls elaborate why do you wish to do so? This will destroy your design timing + fanout opto also if you have done.
I can suggest an automated way - would be to mark all buffers as set_dont_use and perform an incremental optimization - but this may replace all bufferes with inverter pairs
@englishdogg
ya but the above command will reduce the usage of buffers for replacing assign statement.. Replacing assign with buffer for top module is enough.. right..
Even if u change all buffers with inverters we cant see much difference in the area..
We cant completely remove all buffers u need to takecare of feedthrouh paths also...
@nandy
perfoming the above - will it confirm that timing is met or is same before and after this change
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