How to extract the package (bondwire) model after testing?

[lijulia]

package model estimation

How can we extract the package (bondwire) model after testing the chip?

If not, how to modify the LNA VCO design for the next tape-out?

 

[Mazz]

Re: package model estimation

Really hard to do only on measurements basis.
You'll measure s-parameters of your device and try to use a model of the package with some parameters (L,C,R) to fit the measurements with the simulations of the device + package model, but the risk to make mistakes is really high, since you cannot be sure if the differences between what you measure and what you simulate are due to package only, to circuit only or both.
A good experience in modeling packages is necessary, I think.
Good luck
Mazz

 

[lijulia]

Re: package model estimation

Thanks Mazz!

So, you mean, I should simulate the s-parameter of the LNA only without package model, then test the s-parameter for the LNA+pachage together, then use ADS to generate package model to fit the measurement result, right?

But when I simulate the LNA, do I need to put downbond wire in it because I use it for emitter degeneration?

And how to get more accurate package model?

 

[Mazz]

Re: package model estimation

Yeah I see the problem.
So you'll have very different S21 if you have used the wrong package model!
You've got the solution: you should fit the measurements with simulations with downbonding, input/output bonding and so on.
In my experience, if you have leadless package (such as QFN) and you are matched to 50 Ohm, up to 3 GHz you can neglet the package parasitics on input/output, but it can also be very different... depends on many parameters.
The usual way to perform the package modeling is to use a 3D electromagnetic simulator, such as Ansoft HFSS or Q3D extractor (it depends on frequency vs. package dimentions), in which you have to draw the package in 3D and simulate it with input/output ports (could be very hard to compute it).

Another way is to develop some special test ICs (for example with short, open, dummy loads and so on), measure them and deembed the package model, but this is less accurate (due to the inaccuracy of your IC loads).

If you don't have the 3D simulator the old "cut and try" way is the best one: if you have accurate measurements on S-parameters, noise, linearity, in 2 or 3 wafer runs you should be able to optimize your design with package.
Good luck
Mazz