Hi guys,
I am currently simulating 8 bit SAR ADC. I run transient analysis with ramp input voltage and the output is observed as shown in attachment files. The blocks for SAR ADC are included as well. The digital bits out are connected to ideal dac.
From my understanding, the SAR ADC takes 9 clock cyles to finish one conversion (Fclk=5MHz, 1 clock cyle=200ns). The first clock cycle is for reset, and the remaining clock cycles are for SAR algorithm(8 clock cyles). Only at 10th clock cyle the SAR produce a valid output. What puzzle me is that, we only need output at each 10th cycle, the rest is just for SAR algorithm comparison (correct me if im wrong!). So how do I extract the output at each 10th clock cyle so that I can get a nice ramp output voltage. What is the HSpice syntax to do this? My objective is to get a staircase output voltage with ramp-up input, so that I can compare this with ideal ADC and measure INL,DNL,gain error and offset error.
I hope teachers out there can give me some advice.
cheers