How to extract the output at each 10th clock cycle in a SAR ADC simulation?

[snoop835]

Hi guys,

I am currently simulating 8 bit SAR ADC. I run transient analysis with ramp input voltage and the output is observed as shown in attachment files. The blocks for SAR ADC are included as well. The digital bits out are connected to ideal dac.

From my understanding, the SAR ADC takes 9 clock cyles to finish one conversion (Fclk=5MHz, 1 clock cyle=200ns). The first clock cycle is for reset, and the remaining clock cycles are for SAR algorithm(8 clock cyles). Only at 10th clock cyle the SAR produce a valid output. What puzzle me is that, we only need output at each 10th cycle, the rest is just for SAR algorithm comparison (correct me if im wrong!). So how do I extract the output at each 10th clock cyle so that I can get a nice ramp output voltage. What is the HSpice syntax to do this? My objective is to get a staircase output voltage with ramp-up input, so that I can compare this with ideal ADC and measure INL,DNL,gain error and offset error.

I hope teachers out there can give me some advice.

cheers

 

[ablue]

SAR ADC simulation

I think you can latch the output so that the output is available anytime. Also you can use a ideal DAC to convert digital output to analog waveform, and DNL/INL/Gainerror/Offset are all available through the analog waveform.

 

[snoop835]

Re: SAR ADC simulation

Ablue,

How do I latch the output? I don't really get what you mean. And the output of SAR ADC is already connected to ideal dac as you can see in the waveforms (attachment file).

thanks

 

[chenliy]

Re: SAR ADC simulation

I think that if you takes 9 clock cyles to finish one conversion, the conversion is not enough. You must use the faster clock.

 

[ablue]

SAR ADC simulation

You can use flag bit (which flags the finishing of conversion) as the latch signal. if you dont have such bit, you can only use a 1/9 clock as latch signal.

In one word, I think that ur SAR ADC should always latch the data so that the system can fetch output data anytime, also ur adc should have one flag bit to let the system know whether the data is ready or not

sorry, I canot download the jpg.

Ablue