How can i extract the gate- capacitance variation of the MOS transistor, in the Cadence analog design enviroment, dc signal analysis?? Im using the varactor in a LC VCO design, and want to get a good as possible estimation of the ideal LC tuning characteristics.
connect the varactor in simple circuit just the mos and vsin source-make the dc value of the vsin is parameter"ex. put its value-->dc" and put the amplitude a small value "50:100 mv"
-make parametric swee and obsevre the current "u will find the current is varying sinusoiuidal with 90 degree phase with the input source"
-use the calculator to write the relation between the current and the capacitance "find max value of the current and devide it with a constant represent ur freq and the input amp"
-when u make a sweep analysis and draw the calculator fomula u will see the tunning curve