msdarvishi
Full Member level 4
Dear all,
I am using Xilinx Vivado 2016.1 for my design targeting an Artix-7 FPGA. I have written a Tcl scripts in order to create and place some cells and then routing them. Then I managed to do some net delay calculation using get_net_delays command for all corners. Now, I would like to write a part in my Tcl script in order to export those computed delay values directly to an Excel (or any other supported software by Vivado). I did a search and I did not find something about it ! Does anyone can help me to solve this issue, please?
Kind replies and helps are in advance appreciated !
Thanks and Regards,
I am using Xilinx Vivado 2016.1 for my design targeting an Artix-7 FPGA. I have written a Tcl scripts in order to create and place some cells and then routing them. Then I managed to do some net delay calculation using get_net_delays command for all corners. Now, I would like to write a part in my Tcl script in order to export those computed delay values directly to an Excel (or any other supported software by Vivado). I did a search and I did not find something about it ! Does anyone can help me to solve this issue, please?
Kind replies and helps are in advance appreciated !
Thanks and Regards,