zhangljz
Member level 5
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Hello everyone,
I have a question about the sum operation in verilog in modelsim. Here is the code:
The simulation shows sum_1 is 3, sum_2 is 1 which is what we expect.
I can not figure out why they have different behavior
Somebody can help ?
Thank you
I have a question about the sum operation in verilog in modelsim. Here is the code:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 reg sign; reg [1:0] delta; wire [1:0] sum_1, sum_2; wire [1:0] sign_x; initial begin sign =0; delta = 1; end assign sum_1 = delta + sign?3:0; assign sign_x = sign?3:0; assign sum_2 = delta + sign_x;
The simulation shows sum_1 is 3, sum_2 is 1 which is what we expect.
I can not figure out why they have different behavior
Somebody can help ?
Thank you