coshy
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I have a signal with a WNS of 30ns after synthesis on an FPGA with a clock of 16MHZ.
What is the maximum clock that can offset the 30ns WNS?
Considering the WNS 30ns at the current 16Mhz clock, how do I calculate and what is the maximum effective frequency I can expect to offset the WNS 30ns roughly? It will probably be less than 16Mhz, but how do you calculate it? If an exact calculation is not possible, I would like to know how to get a rough estimate.
What is the maximum clock that can offset the 30ns WNS?
Considering the WNS 30ns at the current 16Mhz clock, how do I calculate and what is the maximum effective frequency I can expect to offset the WNS 30ns roughly? It will probably be less than 16Mhz, but how do you calculate it? If an exact calculation is not possible, I would like to know how to get a rough estimate.