I have a question about the pin toggle rate in the figure below:
Fig1. is a power report calculation of pin _165_/A3. When I look at the driver of cell _165_/A3 pin, the toggle rate is 0.1297. How is the value "State Dependent Rise Pin Toggle Rate" 0.002422 estimated when the state condition is "!A1&!A2"? Additionally, how is the value "Rise Pin Toggle Rate" in Fig2. for the state condition "default" estimated?
I have a question about the output pin internal power in PTPX, shown in figure below.
I don't understand how to calculate the Path Dependent Rise/Fall Pin Toggle Rate.
I just know the all the Path Dependent Rise/Fall Pin Toggle Rate summing up is the output pin' s toggle rate.
How does the toggle rate separate according to?