How to establish a continuous output shift REG via VHDL?

[dudleyzty]

Some examples shows that data load needs a clock cycle,but I need one which has continuous output. Pls help me! thx

 

[ydao]

each cycle can do read and output.

 

[dudleyzty]

But only one clock edge in a process, how to do this?

 

[Big Boy]

Not sure exactly if I understand your question.

Do you wish to constantly feed the output to something? If so, you can send the output wherever you wish, after a clock edge, the shifted data is present all the time at register ouput. You can either send it to another flip-flop, or you can do continuous assignment so that the output enter into some logic expression (ex: or'd or xor'd or sent to a LUT or ...).

If you meen that your register load input need to be gated instead of clocked, so that when you 'enable' load, the output follow the input, and then when the 'enable' is de-asserted, the register shift data at each clock edge, I found this example (VHDL and Verilog):

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out.


library ieee;
use ieee.std_logic_1164.all;

entity shift is
  port(C, SI, ALOAD : in std_logic;
        D   : in std_logic_vector(7 downto 0);
        SO  : out std_logic);
end shift;
architecture archi of shift is
  signal tmp: std_logic_vector(7 downto 0);
  begin 
    process (C, ALOAD, D)
      begin
        if (ALOAD='1') then
          tmp  = D;
        elsif (C'event and C='1') then
          tmp  = tmp(6 downto 0) & SI;
        end if;
    end process;
    SO  = tmp(7);
end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out.

module shift (C, ALOAD, SI, D, SO);
input  C,SI,ALOAD;
input [7:0] D;
output SO;
reg [7:0] tmp;


  always @(posedge C or posedge ALOAD)
  begin
    if (ALOAD)
      tmp = D;
    else
      begin
        tmp = {tmp[6:0], SI};
      end
  end
  assign SO  = tmp[7];
endmodule

 

[Aoxomox]

Hi,

i guess you mean asynchronous logic.

If your process is listenning to a clock edge it's called
synchrounous process. all assignments will only be
performed if the checked conditions are true and the
clock has the correct edge.

In case the process is without a clock signal the assignments
a <= b; will be done immediately. Just and, or, xor combinations.
But be carefull!!!

Sometimes it is necessary to implement asynchronous logic
for latency critical reactions. But it's not good design practice.
The signal might be faster but your signals can have unintended
states for a short time. Each element like and, or, not.. has a
different propagation delay. There is always a path through the
logic that is faster than another. So on the transition from one
defined state to another your signal can pass through forbidden
states.

That's why you always should use a clocked process.


hope it helps,

aOxOmOx.

 

[Big Boy]

The above example is took from Xilinx examples (I don't remember exactly which URL).

This use 2 synchronous statement, but synthesize as synchronous clock, with asynchronous load. This is really a synthesizer thing...

It's like writing the same statements with 'clock' and 'reset'. For example (in verilog, I don't know about VHDL...), for a sync register, with async reset, you write
always@(posedge clock or posedge reset)...

This eventually synthesize as an asynchronous reset even though the statement is written to work synchronously with edges. It's the same thing with the example...