How to eliminate "assign" after DC synthesis?

• Aug 25, 2004

• #1

K

kermit

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dc synthesis remove assigns

In my design,some signals like this:
module test ( a,b,...... )
input a;
output b;
......

assign a = b;
endmodule

After synthesis,this statement didnot substitute by inserting a buffer!But this statement cant be recognized by Encounter.
How to eliminate this "assign"?

 

• Aug 25, 2004

• #2

wadaye

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set_boundary_optimization * assign

Hi kermit:

You can use "set_fix_multiple_port_nets" to solve this problem!

wang1

 

• Aug 25, 2004

• #3

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khplnarayana

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Hi,

I tried the suggested fix couldnot do it. Can you please elaborate on this.


Thanks,
Narayana.

 

• Aug 25, 2004

• #4

M

Memphis

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After setting "set_fix_multiple_port_nets" true, you have to resynthesis and write the verilog out, then you will get the netlist without "assign". Hope this suggesstion is helpful to you.
:wink:

 

• Aug 29, 2004

• #5

E

eternal_nan

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Make sure you invoke the command with the following options:
set_fix_multiple_port_nets -all -buffer_constants

Missing the -buffer_constants could cause you to still have some assign statements. Also, make sure you are not doing a "set_dont_touch" on some of the modules that contain assign statements...

 

• Sep 4, 2004

• #6

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troops

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i meet the same problem,

if u can't remove assign , edit it directly ......

 

• Sep 4, 2004

• #7

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microww

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when you have tri_state bus or ports ,you will have "assign ";or when you have some unconnected pins ,you will have the "assign ".
You can add boundary_optimization and set fix to remove the "assign"

 

• Sep 6, 2004

• #8

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horzonbluz

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Hi, microww.
“set_boundary_optimization true”
This compile setting is not used. It could change the logic of your subdesigns. So we do not use it in DC.

 

• Sep 7, 2004

• #9

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ic_design

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"edit it directly" is not the best method. you had better use "set_fix_multiple_port_nets".

 

• Sep 7, 2004

• #10

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farmerwang

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set verilog_out_no_tri true
set_fix_multiple_port_nets -all -buffer

This should fix your problem. Note, you need to apply this for every design your read.

 

• Oct 14, 2004

• #11

S

seanwu

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It seems no problem, when use assign to change net name in a module.

 

• Oct 14, 2004

• #12

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ecijun

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One book say it incompatible with "some" P&R tools, but I did not meet this problem, I use SE and Soc Encounter.

 

• Nov 3, 2004

• #13

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carrie

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use ' change_names -rule verilog -hierarchy ' before write out verilog format netlist.

 

• Nov 5, 2004

• #14

maxsnail

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set verilog_out_no_tri true
set_fix_multiple_port_nets -all -buffer

 

• May 31, 2011

• #15

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poluekt

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Carrie, best thanks. Using "set_fix_multiple_port_nets" without "change_names" I couldn't remove "assign" from netlist.