I have the PSPICE model of an Buffer...
what value i need to change so as to reduce its propagation delay.
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Code:
*----------------------------------------------------------------
* 74ALS1034 Hex Drivers
*
* The ALS/AS Data Book, 1986, TI
* atl 7/28/89 Update interface and model names
*
.subckt 74ALS1034 A Y
+ optional: DPWR=$G_DPWR DGND=$G_DGND
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf DPWR DGND
+ A Y
+ D_ALS1034 IO_ALS000 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.ends
That is not the buffer model, it's a subcircuit that has a
buffer model ('buf') called out in it. You need to edit 'buf',
or properly set the delay param, but I don't think you can
go lower than the 0 value it already has (meaningfully, if
functional / parseable at all).
Your "prop delay" in a 1-layer CMOS gate is almost entirely
the half-risetime of the current-constrained output against
its capacitive load. So you may need to change one or the
other of those. A buffered gate of course has a series of
these, most of them fixed-internal-load (and if you had
such a detailed model, those drives and loads might want
some fiddling too).