how to dump very long time simulation in modelsim VHDL?

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roger

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dumping signal in modelsim vhdl

as title,
If I dump as usual, the fsdb file will be huge,
how to dump them by splitting time & different fsdb file.
 

modelsim $dumpvars

I think you may dump the specified signals to your database file, not dump all signals in all heri .

I don't know if the Modelsim support the "$dumpvarson/$dumpvarsoff". If it can use those task, you can use those to specify the time period in your simulation.

Best regards.
 

fsdb dumpvars modelsim


Yes, these two systemcmd are supported by modelsim. They are

standard verilog systemtasks, so every veilog-simulator should support

them.

And I think your way can work.
 

modelsim vhdl now time

The problem is not a long time dump . The Window file system can not biger than 2GB so the FSDB file can not biger than this


You can just download the signal you want . Do not dump all of your signal in your design
 

splitting an fsdb file

All guys are right.

You can use the system task "$dumpvars" to dump the signals of your need.

$dumpvars
Specifies the nets and registers whose transition times and values you want simulation tools to record in the VCD file you specify with the $dumpfile system task.

$dumpvars(level_number,module_instance | net_or_reg);

You can specify individual nets or registers or specify all the nets and registers in an instance.
 

modelsim simulation time vhdl

all guys went wrong!
windows system can allow 2GB size is right.but that's not the point
actually modelsim did support time slot dumpping.

just from the manual

page 519

B.R :roll:
 

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