how to draw rtl of a verilog code?

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gstekboy

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Please help me,how to draw rtl of a circuit inferred from a fragment of verilog code.
 

RTL is Verilog code.You don't draw it, you write it.

Please re-phrase your question.

r.b.
 

An assignment question.
Well you're supposed to work out what the circuit is from the written Verilog. There are many code templates for things on the net.
 

gstekboy said:
Can i draw it by using mux
Click to expand...
Start off by breaking down the problem into manageable and comprehensible pieces and what is obvious:

We know we have "inputs", "outputs", "an ALU", "some combinatorial logic" that controls the output of the signal.

We *need* to know how to implement the combinatorial logic, to control if the output is from the ALU or is 8'b00000000

A mux will be needed.

Now how to implement the control logic? You can draw a truth table to help figure that out. Also, you can use a Karnaugh Map to reduce the control logic into the minimal number of gates.
 
Rtl is a highlevel modelling is it possible to implement using gates?
 

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