How to do proper biasing?

[aryajur]

When designing an amplifier stage, I assume some currents in the branch and do my hand analysis. When I try to make and simulate the thing in cadence I set the Gate voltages so that I am at the operating point I designed the amplifier or at the operating point we have the best gain. But then suppose I cascade another stage to this, what should be the best strategy to design, or rather assume the biasing current in that stage, because now the problem is I do not know the biasing gate voltage that the 1st stage output will produce, since hand calculations cannot calculate the Vds accurately, and they are sensitive.
One solution that obviously comes to the mind is try to set the current by making current sources to define the current, but I seem to be having a problem with that, because the PMOS of the technology cannot source much current, and somehow it is defined by the input biasing voltage of the NMOS of the stage.

Any insights, suggestions, discussions would be greatly appreciated.

 

[lastdance]

Hi
PMOS unable to source the current??
How much current are you designing for?
I am unable to visulaize what you have mentioned? Am I right to say that you have a NMOS common source as a first stage loaded with a PMOS current source and a second stage of another NMOS current source? And you are having problem biasing this stage bcos somehow you need high current unable to be sourced by regular PMOS?
you may want to post your schematic here, it's unclear to me why are you having problem?

 

[aryajur]

Let me rephrase the question. Suppose I want to have a particular biasing current in a secong stage common source (NMOS input). Then how do I go about setting that current?
Since if I try to set the current through the PMOS current source biasing it doesn't give work properly since for this current source common source the NMOS below is also strongly (perhaps more strongly) controlling the current due to its biasing Vgs from the previous stage output voltage. And the thing is I cannot know this output voltage or set it reliably.

 

[terryssw]

Suppose in your second stage you have NMOS common-source amp and PMOS current source load. Then your second stage biasing current is mainly controlled by the PMOS current source, and actually Vgs of the NMOS is determined by this current. However if the opamp is used as a feedback amplifier, the common-mode feedback will automatically adjust the Vgs of the NMOS to a suitable value (and this also is your design value).

So as a summary, in designing second stage, you just need to design how much current in the PMOS active load, and also have a correct CMFB circuit, then the Vgs of NMOS is automatically set, and you no need to explicitly specified this Vgs by previous stage output.

Do you simulate your opamp in openloop or closed loop? You must simulate it in closed loop to make the feedback active. If you simulate it in openloop, normally the output at the 1st and 2nd stage will be pull up or down into VDD or gnd. Also, the output voltage will be extremely sensitive to process variations since you do not have feedbacks.

 

[lastdance]

Q:
1. is this 2nd stage intended to be a Class AB output stage?
2. if so, r u talking about how to set up q current?
3. IF not, again, I missed something.

Assuming you are designing an output stage and you want to set up a q current for the output transistor.
You can refer to Gray and Meyer's book (and some papers) to see how's the q current for the power transistors at the output stage set up. Your driving signal needs to be composed of two elements, one to determine the strength of the drive and the other to set up the q current.

 

[ambreesh]

We are talking openloop here, hopefully.
Your current of secind stage is fixed by the PMOS current source. Tweak the first stage sizes to get the output voltage that would enable your second stage NMOS to sink the same current as PMOS is sourcing.
Your gain from first stage may fall.
Read on systematic offset in John Martin