girih192002 said:
Hi Guys,
I did RCX extraction of my design and i have generated av_extracted view of layout and i can see parasitic Resistance and Capacitance in that View. I would like to do Post layout simulation of that view.
can any body tell me how to do post layout simulation with av_etxacted view in Analog Design Envirnment (ADE). I read some where on net we can do simulation in this way also. there is no need to use netlist.
Perhaps this Cadence tutorial from
shashikumar.22's posting on Thu, 14 Jan 2010 11:24 (4.rar) may help you. See at the end, after
Design Verification: Post Layout Simulation.