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How to do Post Layout SI using Diptrace

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pal114525

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Hi,

I'm new in PCB design. I've done a layout which DRC clean. It is a single layer board.
Can anyone please tell me how to do Post layout SI using Diptrace?

Thanks & Regards.
 

SI Analysis on a single-layer board ? are you serious ? why is it needed ?... moreover I just saw the DIPTRACE website for their products. I don't think they have a dedicated SI tool..
 
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SI Analysis on a single-layer board ? are you serious ? why is it needed ?... moreover I just saw the DIPTRACE website for their products. I don't think they have a dedicated SI tool..

Hi,

Thanks for your valuable feedback.
Would you be kind to tell me, " For how many layers SI is required and which tool is the best suitable for that?"

Thanks & Regards.
 

What signals do you have that you need to run SI?
The cynicism is because signals that require SI have to have controlled impedance layout and that cannot be achieved with 1 layer... 2 (one layer providing a contiguous return path) is an absolute minimum for the simplest of designs that would require SI and a layer count of 8+ is far more common.
More info is required.
 

What signals do you have that you need to run SI?
The cynicism is because signals that require SI have to have controlled impedance layout and that cannot be achieved with 1 layer... 2 (one layer providing a contiguous return path) is an absolute minimum for the simplest of designs that would require SI and a layer count of 8+ is far more common.
More info is required.

Hi,

Thanks for your valuable feedback.
Would you please tell me which tool is the best for SI analysis?

Thanks & Regards.
 

Do you have any clock signals in your PCB?

I have never faced a scenario of doing SI for single layer PCB's. The layer which we used for SI is 4 layer that too only for the clock signal we did that.

The maximum we tried is with 10 layer where the board had DDR, ethernet and more clock signals.
 
Do you have any clock signals in your PCB?

I have never faced a scenario of doing SI for single layer PCB's. The layer which we used for SI is 4 layer that too only for the clock signal we did that.

The maximum we tried is with 10 layer where the board had DDR, ethernet and more clock signals.

Hi,

Thanks for your valuable feedback.

With Regards.
 

There is a option of as Helped Me for each post... If you feel really helped then you can simply click that instead of typing a message. Both things will convey same meaning.

Thanks
 

If u google tools for SI analysis u will get multiple results.
Cadence -allegro-PCS SI-Sigrity
Mentor Graphics
Altium

How much complex u r board is, what are the interfaces are , speed of the interfaces, Type of analysis u r doing..etc will determine your SI tools requirement.

There are multitude of free tools like
LTSpice
TINA-TI
few things for Linux...
 
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