How to do gate level simultaion under on chip variation analysis mode ?

[owen_li]

Hi.

I just came up with a question about the gate level simulation.
when coming to deep submicron technology, we would like to use ocv analysis type to do STA.
So, when generating the sdf file, it will have three different delay values, like max/min/typical delay for a cell.
As we know, STA tool will choose the worst case to analyze timing when using OCV.
Now coming to gate level simultation using sdf file, will simulation tool choose the mix delay values, like maximum delay at data path
mimum delay at clock path, when doing setup analysis ? If so, how will simulation tool covers the hold analysis.

I am sorry that I am a backend engineer, and don't have some ideas on frontend.

Thanks all!

 

[owen_li]

If I remember correctly there are three options to select from the SDF. To be on the safe side you have to run all of them.
Gate-level simulation runs very slow so this might be a tedious task.

I did for an FPGA project, (FPGA SDF files sometimes have all the three options the same) :
"The net-list and SDF are generated using netgen command:
netgen -sim -ofmt vhdl test.ncd
Two files are generated: test.vhd and test.sdf...."


Thanks, pini_1.
What do you mean about "To be on the safe side you have to run all of them" ?
Shall we run the mixed mode, like max delay on data path, and min delay on clock path ?

Thanks!

 

[honey13]

Hi owen_li,


We need to run the sdf simulations at both MIN and MAX corners. Hold checks can be done during MIN case analysis.

 

[owen_li]

Thanks honey13 and pini_1!
I think you didn't catch my question.
What I want to know is whether we run gate level simulation under mixed sdf. For example, data path use max delay in sdf, clock path use min delay in sdf, for setup check.
coz, when doing STA, we have an On Chip Variation mode, it will calculate the max delay for data path, and min delay for clock path when checking setup violation.
If we just apply three sdf values (max, min, typ) independently, I think it will not create the worst timing scenarios.
And gate level simulation will be more optimistic than STA.

Thanks all!

 

[ramkka]

HI,
with OCV

setup : launch delayed and capture made faster
Hold: Launch is faster and capture delayed.

Thanks,
ramkka