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How to divide clock by 4.5 with 50% duty cycle

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niks

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can anyone tell me how to divide clock by 4.5 with 50% duty cycle, with minimum amount of HW/flops
niks
 

Clock divider

Hi Niks, what is your clock frequency?

Tornado
 

You can multiply by 2 and then divide by 9.

1) Multiply by 2, use a DLL (DCM) in a Xilinx part
2) Divide by 9, use two 1/3 dividers in cascade:

To divide by 3 with 50% duty cycle you need:
2FFs and some gates, there is an App in Xilinx about how to do a divider by 3 in a CLB (2FFs and a LUT for some old Xilinx families), search for it, hopefully is still there.

So with: 1 DLL + 4FFs + 2 LUTs you have a 4.5 divider.
I have never tested or tried but it should work.

If you need the divide by 3 circuit give me a shout but googling you should be able to find it.

Regards,
 

its depends from your clock frequency and hardware you want to use
 

When frequency goes high, the duty cycle could be away from 50%, please be carefully !
 

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