Hey Danesh
What you essentially need a frequency/10 circuit.
If you do not need 50% duty cycle then ring structure can be a solution :
-connect 10 d f/f in series taking q of last to d of first
-load '1' in any one f/f and '0' in rest
-provide 100 MHz clock at the input of all flops
-take output at any d
take 5 d flip flops.... conncet d flip flop as T flipflop... preset all flip flops...
for firt flip flop give 100MHz input, for second give the ouput of 1st. for 3rd give o/p of 2nd... like that...
finally u will get output of having frequency of 10MHZ.....
Using 5 FFs will result clk/32.
It seems that without combinational logic it is impossible to divide clk by 10. To minimize combinational logic a 3-bit LFSR can be used. Also an extra TFF with enable is required.
The last three flip-flops form a divide by six Johnson counter,
if you add two more flip-flops you'll get a divide by 10 counter
with a duty cycle of 50 %. The first flip-flop with the 74LS86
gate was necessary to generate a clock pulse for the flip-flops
at any transition of the input signal because the Johnson counter
divides by six and the complete circuit should divide by three.
Hi danesh,
First divide the clock by 2 using T f/f (From D f/f), then use divide by 5 ckt to get 10mhz clock. The idea for designing a divide by 5 ckt is generate two clocks which are 180 degrees phase to each other from 50mhz and ORing them, each derived clock will be having duty cycle two clocks high and three clocks low.
other clock will be inverted of this clock.