[SOLVED] How to disable refresh on the Altera DE2-115 SDRAM

[I_THINK_ITS_SHORTED]

I'm working on a project and I need to completely disable the refresh of the Altera DE2-115 SDRAM, which would allow me to measure retention time of the SDRAM cells.

So far I have tried modifying the SDRAM_REFRESH_PERIOD in Qsys under the SDRAM timing settings. I tried setting it to 0, and I also tried setting it to very high values.
I then tested the SDRAM memory retention and regardless of the what I set SDRAM_REFRESH_PERIOD to it retains any data I write to the memory.

What I want to happen is that when I write to the memory, the bits revert to their previous state over time, since the capacitors are not being charged via a refresh.

Any help with this would be much appreciated.

 

[FvM]

Guess the device is performing self refresh when left idle.

 

[FvM]

Self refresh was just a guess, I see that CKE has to be released to activate it, this doesn't happen in Quartus SDRAM IP. Literature suggests however, that SDRAM content of most cells may be retained at low temperatures even for minutes.

You can look into generated files to see how the refresh period is actually changed with IP settings. The SDRAM controller core doc doesn't specify supported refresh cycle settings, but refresh_counter size is 14 bit and value of 0 sets just the maximum cycle of 164 us. To disable refresh completely, you need to manipulate the generated HDL file xxx_sdram.v.

 

[I_THINK_ITS_SHORTED]

This is the info I needed. I'll look into the refresh logic in the Verilog file and see what modifications I need to make to prevent refreshing. I also found the datasheet for the sdram, which includes truth tables showing which signal combinations correspond to the refresh functions. Between the two I should be able to figure it out. Thanks for your help.