Basically the AND gate is made of a NAND gate + an inverter stage.
Usually the NAND gate transistor sizes are common to all drive strengths, and the inverter stage has an adapted drive strength.
For example:
- x1 : has an inverter stage with NMOS with W=1u and PMOS with W=2u
- x2 : has an inverter stage with NMOS with W=2u and PMOS with W=4u
- x4 : has an inverter stage with NMOS with W=4u and PMOS with W=8u
Thanks for your reply. So I dont need to add anther nand gate from the output of the 1 st nand gate?
I assumed that I need to have 2 outputs from the first Nand Gate and each output will have a nand gate respectively.