How to determine Vth from this nmos graph.

[imperza]

Hi, recently I simulated nmos characteristic and obtained this graph. Unfortunately anthena silvaco tool that i had only can give Id vs Vg graph. How do we determine Vthreshold?

Vds is 0.1v
Thank you.

 

[Junus2012]

hello
from the definition, the threshold is the gate-source voltage at which the transistor start to conduct the current on it its drain. this is about 0.5V in your graph.

any way the exact value of the threshold voltage still not fully defined as the transistor even start to conduct before this voltage in what we called sub threshold voltage. but inyour case 0.5V is ok to consider it as Vth

 

[imperza]

Thank you Junus. Do you know how to determine leakage current for the nmos device using tonyplot etc.? I need to have less than 0.1 nA leakage current for the device.

 

[Junus2012]

Hello imperza

connect the drain to Vdd and apply a zero gate-source voltage, measure the drain current which represent the leakage current.

- - - Updated - - -

in your circuit if you are not sure to have zero Vgs, then repeat the last step with the minimum Vgs (which is less than Vth) you can have

 

[imperza]

Thank.
Ive tried with silvaco tool's extract command.
And I've got this value.

"leak=4.75321e-05 A/um"

Is it in standard unit and possibly around standard value?
I need to tune it to <1nA

 

[Junus2012]

Hello

I dont know what mean the A/µm.
in general if you are not using deep submicron technology then you will not have a problem. for example me I am working with 0.35µm technology and I never take care about the leakage current coming from the tunneling effect on the MOS oxide.
to be more accurate the subthreshold current is also contribute to the leackage current therefore I suggest you to use the method I told you

 

[imperza]

Ok.
Based on your explaination on finding leakage current on #4.
"apply a zero gate-source voltage"

Im bit not understand of how to make it work on my tool. This is how it appear on my command. The vgate is initial voltage bias, vfinal is final gate voltage bias.
do we need to make both vgate and vfinal =0?

solve name=gate vgate=0 vfinal=3.3 vstep=0.1

 

[Junus2012]

you can keep Vgs constant at zerowith no sweep, rather you can sweep the drain voltage from zero to VDD and monitor ID. is it clear now?

 

[Kenneth_Potter]

You could plot the subthreshold slope - Log (Id) vs Vg. Then read off the drain current when you have zero volts on the gate. it should ideally be somewhere around 1e-12 depending on technology and threshold voltage.

Best wishes, Ken.

 

[dick_freebird]

You could export tabular data to Excel and fit the sqrt(Id)
vs Vgs line. Or you could just call some arbitrary current
level your "VT" (but this would not be the VT you want to
insert in a model card, exactly). There's a bunch of VT
extraction methods, giving slightly different results and
resiliencies to measurement conditions & device nonidealities.
What your use is for the VT value, might indicate which one
you prefer (process control in-line wants different things
than SPICE modeling, etc.).

 

[Kenneth_Potter]

Hi Imperza,

Attached is a pdf which discusses various techniques for extracting threshold voltage as dick has mentioned each of these techniques will provide a slightly different value for threshold. The key is to use one and keep with it for measuring all your devices. I have used the second derivative method in the past but you would need to use some software to calculate the first and then second order derivatives so this might be more time consuming. The constant current method is also popular and faster. There are other communications within the IEEE if you have access which discuss the merits and draw backs of each of these techniques based on geometry and operating point.

Hope you enjoy your analysis, Ken.