How to determine the input value???urgent!!!

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Thanks for your advice~~~
I have correct it and i have gt the correct ac response~~~





After that,i also try for 3rd order low pass OTA-C filter...





In testbench, the 1st order filter is the schematic of 1st order filter...
Do you have any suggestion for it to operate low power???
 

The main problem that I see is that NM2 is not matched well with NM3, in terms of drain voltage.

If you annotate the operating points you will see that the NM2 current will be much lower than NM3.
You can try making the input dc voltage 800mV instead of 600mV and/or enlarging the NM0 and NM1 ~ 10x maybe.
Then you will have to lower the bias current a bit in order to have the same current flowing the OTA as you had before.
 
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for this circuit,i need to draw layout...how i make Ibias for layout???
Do u hv any suggestion for me??

- - - Updated - - -

for this circuit,i need to draw layout...how i make Ibias for layout???
Do u hv any suggestion for me??
 

You don't make layout for the ibias. The source is not on-chip, it is one of the measuring equipment.

You just put a ibias pin at the drain of NM3.
 

so i no need to make the current bias circuit for the input ibias if i want to draw layout for this circuit??
 

how to make this filter circuit for 3rd order in layout design???
and how to make the circuit design in low pwer application??
 

You already made the circuit in the schematic. This is the circuit you must do the layout for.
Make the layout of one OTA and then put 3 of them in series, just like your schematic.
 
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if i want to replace the ibias input with transistor, how i make the current bias circuit on the circuit???
 

Use a resistor from vdd to ibias pin. Change the value until you get the current you want.
 
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if i want use the transistor??PMOS or NMOS i should use it..and how to replace the current source..??
 

according to the schematic you presented you may use:
1) just resistor to vdd (as it was already pointed out by lamoun).
2) if you want to go for something less dependent on Vdd, you may look at Widlar current source or Vth current source. which are simple to implement. the last one is quite independent on vdd variation. both employs only mos devices and couple of resistors.
 

hihi..i have done for the schematic...bt i hv a lot of problem on layout for this schematic..

1. Do anyone know that what is the silterra 013 rule file for cadence for DRC simulation?
2. For my circuit what layout techniques (eg: interdigitated devices, common centroids or else) can be used for drawing layout?
3. Do any technique for automatic layout from schematic?
 

if u share schematics would be easier to suggest layout strategy.
in general there is no real solution for automatic layout. you can instantiate transistors/res/etc... with already proper dimensions directly from schematic. this will make your life a bit more simple however then you would have to connect them manually.
 

Thanks for the reply~~~
Here i have attached my schematic..
1. single stage OTA-C filter


2. 3-order OTA-C filter


Then i f want to run DRC..what is the rule file for Silterra 013 technology..??
 

well and how critical is matching in your application ?
1) diff pair
- use fingers.
- do not forget about dummies (d)
- common centroid is the best approach (normally). share sources or drains of transistors when possible. you may use simplified structure of common centroid: like 2112. or with more fingers (1-finger of the first transistor of diffpair, 2 - of the second one).
in general very good structure for matching differential pairs:
d2211d d2211d
d1122d d1122d

2) for current mirrors you can also use common centroid. here you have CM 1:1 - so just use equal number of fingers. in general for matching current mirrors you also should take care about current direction in fingers - but here should not be critical

regarding DRC problem - i do not know
 
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if i want to check the noise figure and power consumption of my circuit, which analysis i can use and how to use it??
 

Hi everyone,

Could anybody teach me how to get the noise figure and power consumption of OTA-C filter by using cadence 0.13um technology?? what analysis in cadence i can use and how to use the analysis??

Thanks~~~
 

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