There are several papers on the internet on this topic -
BGAs can be successfully desoldered/resoldered by reasonably competent assembly shops, but there is always some risk involved, dependent on the pitch and ball size of the devices, the quality of the PCB fabrication, soldermask material, aperture, pads and via sizes&locations, copper weight, etc.
Visual indpection and X-ray of the assembly can catch the more blatant/obvious ones, especially near the outer edge, but is otherwise pretty limited.
It seems a number of designers are incorporating some BIST (Built In Self Test) techniques to help address the issue/detect inferior joints (or potentially detect failed joints in the system after it has deployed). In the simpler case, it involves adding some capacitors tied to I/O pins on the device at strategic port locations and measuring the ability to charge/discharge the capacitor through external probe tips contacting various I/O test pads on the PCB, but it may not require any FPGA code additions to test in the unpowered state in production. In a more complex version, some BIST FPGA code is dedicated to check for high or low logic levels on I/O pins when a self test mode is initiated, and it may use the external, added capacitors or resistors as the test loads. I don't think that either of these cases can guarantee 100% identification rate, though, but certainly it makes sense to design in some minimal level of BIST capability as components complexity and number of connections grows higher.