How to desing low quiescent current LDO

[jutek]

ldo low quiescent current

Hello!

I need some informations about low quiescent current LDO regulator.

What should i start from and what topologies of opamp and pass device will ensure low power dissipation. What additional circuits do i need else? I also need high PSRR and fast response. Reference voltage comes from outside circuit.

Regards

 

[rfsystem]

opa quiescent current

I did not design it before but the output stage is a PMOS. The trick is possible to adjust the bias current of all stages proportional to the output current. So the regulation speed slows down with low current but the total current efficiency could be made high over a high current range.

 

[jutek]

low current ldo

I did not design it before but the output stage is a PMOS

yes, the pass device is a PMOS transistor cause it can be turn on with a quite low voltage. should i use only PMOS transistor or some kind of buffer between opamp's output and PMOS gate?

The trick is possible to adjust the bias current of all stages proportional to the output current.

yes, but how to do it?

regards

 

[rfsystem]

quiescent current ldo

I did not have a schematic entry now. I consider to split the PMOS LDO driver into the main drain output and a second small pilot current output. Gate and source are equal. Make shure that the drain voltage is equal to the LDO output. Use a cascode and drive the gate of the cascode so that the drains are equal. This pilot current could be used to drive mirrors and diffstages of the regulator. So a kind of adaptive speed regulator. The current used in the mirror are defining the speed of the regulator.

Hope that helps w/o schematic!

 

[jutek]

Hope that helps w/o schematic!

not really yet, but i'll try to imagine it in the higher order of abstraction

if you find sometime the schematics i'd be very grateful

 

[andy2000a]

low quiescent current LDO regulator
how low current ?? 1ua or 0.1ua ??

we can easy design OPA or bandgap work on < 10ua .. if you want let you LDO work on < 1ua , maybe bandgap have some problem . for small current and Vbg keep 1.2v you need large "resistor" in chip .

 

[jutek]

low quiescent current LDO regulator
how low current ?? 1ua or 0.1ua ??

as low as possible, it has to be optimized for minimum power

I don't bother about bandgap cause i don't design it, i have 0.8V specified and given from outside circuit.

what topologies do you recommend for low power supply (1.3V) and high PSRR and low quiscent current