Danielye
Junior Member level 3
pp1s gps
The following is the architecture of PLL
Input Reference -> PP1S from GPS receiver engine:time accuracy500ns
Phase Detector -> JK-Flipflop or other kind PD by FPGA
Loop bandwith filter -> narrow-band digital filter,bandwith is tunable,
DAC -> By FPGA Δ-δ DAC, PWM mode
VCO -> By high stable OCXO 10MHz
The questions are as follows,
1. what comparison frequency is better? 1Hz or 2KHz
2. which kind of Phase detector is better in this case?
3. How can I ensure that the PP1S output (from OCXO output Divided by 10M) is aligned with PP1S from GPS when the PLL is locked. In other words, the steady phase error is zero. Is this determined by the PD detector or the order of loop filter?
The following is the architecture of PLL
Input Reference -> PP1S from GPS receiver engine:time accuracy500ns
Phase Detector -> JK-Flipflop or other kind PD by FPGA
Loop bandwith filter -> narrow-band digital filter,bandwith is tunable,
DAC -> By FPGA Δ-δ DAC, PWM mode
VCO -> By high stable OCXO 10MHz
The questions are as follows,
1. what comparison frequency is better? 1Hz or 2KHz
2. which kind of Phase detector is better in this case?
3. How can I ensure that the PP1S output (from OCXO output Divided by 10M) is aligned with PP1S from GPS when the PLL is locked. In other words, the steady phase error is zero. Is this determined by the PD detector or the order of loop filter?
