how to design the comparator?

i am designing the comparator which is used in the pipeline ADC.but i don't know how to choose the capacitor parameter. you know ,for the capacitor, the thermal noise is the main consideration.the ADC is 14-bit,and i am designing the first stage,it is 4-bit,and one extra bit is used to do the digital correction.

speed, offset, slew rate, power and so on

You mean the kT/C noise? What has to do the capacitor with the comparator?

the capacitor is used to sample the input signal.
how to determine the resolution of the sampling for the condition
14-bit the total resolution and this stage is 4-bit.

ocarnu said:

You mean the kT/C noise? What has to do the capacitor with the comparator?

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Your concern is certainly valid because the capacitor needs to be chosen wisely to overcome the kT/C noise limitation since you are dealing with 14-bit system. Even though there is some gain (2^4=16) in front of your comparator, I would still recommend that you chose the capacitor so that kT/C of this comparator is at least 12-bit (or 72dB) lower than your full-scale signal so that it does not become a limiting factor in your overall SNR budget.

i think i should decribe my problmes in detail.
my project is a 14-bit pipeline ADC.and now i am designing the first stage.
which is a 4-bit,one extra bit is used to do the digital correction.so the residual gain is 8(16/2).for one extra bit,so the offset of comparator we can tolerate is about 60mv.so i think we only need the samling resolution plus the offset of the comparator is samller than 60mv?
is it correct for my understanding?

willyboy19 said:

Your concern is certainly valid because the capacitor needs to be chosen wisely to overcome the kT/C noise limitation since you are dealing with 14-bit system. Even though there is some gain (2^4=16) in front of your comparator, I would still recommend that you chose the capacitor so that kT/C of this comparator is at least 12-bit (or 72dB) lower than your full-scale signal so that it does not become a limiting factor in your overall SNR budget.

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Hi.
You are designing a 14-bit ADC so theoritically
SNR(max) = 6.02*14 + 1.76 =86.04dB
Then you should choose the desired noise+distortion power. e.g. if this equals quantization noise power, the whole SNDR will decrease by 3dB. So the whole ADC SNDR should be about 83 dB. Now you can calculate noise power for each stage and if you have chosen each stage resolution, the only unknown value in noise power will be CF (feedback cap. in residue stage. Since you can express other capacitors in terms of CF). By equating these two expressions (desired SNDR and VFS^2/8/(Vnq^2 + Vnith^2) ) the value for CF will be calculated. But don't forget the scaling factor for CF in next stages (from the first stage to the last one, CF value will be decreased, since the contribution of each stage in the total ADC error will be decreased in last stages.)

Regards,
EZT

what is the meaning of the "Vng" and "Vnith"?

ezt said:

Hi.
You are designing a 14-bit ADC so theoritically
SNR(max) = 6.02*14 + 1.76 =86.04dB
Then you should choose the desired noise+distortion power. e.g. if this equals quantization noise power, the whole SNDR will decrease by 3dB. So the whole ADC SNDR should be about 83 dB. Now you can calculate noise power for each stage and if you have chosen each stage resolution, the only unknown value in noise power will be CF (feedback cap. in residue stage. Since you can express other capacitors in terms of CF). By equating these two expressions (desired SNDR and VFS^2/8/(Vnq^2 + Vnith^2) ) the value for CF will be calculated. But don't forget the scaling factor for CF in next stages (from the first stage to the last one, CF value will be decreased, since the contribution of each stage in the total ADC error will be decreased in last stages.)

Regards,
EZT

Click to expand...

it's very useful, who can give a further talk

Hi.
"Vnq" (Q not G) represents quantization noise power and "Vnith" represents input-referred thermal noise power. both of them have a power of 2, in order to change the dimension from voltage to power.
As you know, Vnq^2, for a uniform distribution of quantization noise with zero mean value, is VLSB^2/12.
For Vnith, if we assume every stage has a total noise power equal to Ai×KT/Cfi which is referred to the input of the i-th stage. Where Cfi is the feedback capacitor of i-th stage and Ai is the proportionality factor, which may varies for each stage. Then
Vnith^2 = A1×KT/Cf1 + A2×KT/(Cf2×G1) + A3×KT/(Cf3×G1×G2) + ...
where Gi is the gain of i-th residue stage in the pipelined structure. We divide each stage input-referred noise by the total gain of its previous stages in order to calculate the input-referred noise of the whole ADC, which is the input of first residue stage. (remember! in this calculation we have assumed there is no S/H stage at the front-end of pipelined ADC. If there is, we should consider its contribution to the whole noise power.)

Regards,
EZT

dear ezt:
first,thanks for your help.but i want to konw why you only consider the thermal noise of Cfi,i think the Cs and Cref(the capacitor is used to sample the Vref) also contribute to the noise.
and i found you tell me the solution to choose the capacitor's parameter for the residual amp,but how about the siwtch-cap comparator,you know,for the comparator,Cf is not used.only Cf and Cref are used.
if you are convenient,i hope you can read the Iuri Mehr and Larry Singer's paper:<A 55mw,10-bit,40Msample/s Nyquist-Rate CMOS ADC>.please tell me how to choose the Cin and Cref 's paramter of the MDAC and flash comparator.
thank you agin