How to design the basic PLL charge pump?

Hi everyone,
please i am trying to design the basic PLL charge pump (found in razavi's book, p.565) which consists of two current sources and two switches. The problem i am having is with the biasing of the transistors to behave properly. I have biased the topmost PMOS to act in saturation (as a current source) with a gate voltage, Vg, of 1v and Vs (vdd) of 3v. The 2nd PMOS which is the switch has a Vg of 0v, representing the logic level 0. (i' expecting the switch to be on). I know for it to act as a switch it needs to be in triode, but i'm unable to move it into triode without changing the gate voltage. I was thinking increasing W/L should be able to achieve this, but that is not so in simulation. Please, how do i proceed?

And if i'm going about it totally wrong, then how should i bias the transistors to get the top PMOS and down NMOS acting as current sources and the the other two as switches. Please and please help me.
(i'm new to analog design, so please pardon my ignorance)

Angelina123 said:

... to get the top PMOS and down NMOS acting as current sources and the the other two as switches.

Click to expand...

Hi Angelina,
I'd think you should increase the W/L ratios of the current source transistors above those of the switches.

erikl said:

Hi Angelina,
I'd think you should increase the W/L ratios of the current source transistors above those of the switches.

Click to expand...

thanks very much for the response. the truth is that i have actually tried that, but it moves the current source transistors rather into triode, and not the other way round. Am i doing something wrong?

Angelina123 said:

Am i doing something wrong?

Click to expand...

Don't know. You should show your circuit including W/L and bias values, stating your process resp. used models.

check this diagram...

i checked your schematic , but did not recognize which one belong charge pump , which one is PFD, VCO , LPF, could you show me by mark on it ?

View attachment New OpenDocument Text.pdf

check this document...

exactly the kind of guide i needed. Thanks.

It is not a good idea to go totally tristate near lock equilibrium. You will usually always end up with a float hole in the phase lock range of a couple of degrees that adds noise to the loop. A little pull down bleed during lock condition keeps loop out of the floating hole.