how to design SHA for pipeline ADC ?

[flesher]

Hello guys, some question about pipeline ADC Front end SHA?

1, what's the capacitor mismatch requirement ?
I found that many thesis say ΔC/C< 1 LSB, why it isn't 0.5 LSB? If the ADC resolution is N, ΔC/C<1/2^(N+1) or 1/2^N?

2, how to do the AC simulation for the OTA used in SHA?
I know ,for the stability ,we should simulate the loop gain( Af) and phase to verify the PM is enough or not. But the feedback capacitor(Cf) connects the input and output of the OTA. how do i open the loop? why?

I found many thesis just open the Cf and let the Cf to be the OTA loading( of cause , the loading include other's capacitors) , then simulate it. But I think it looks like doing the open loop simulation for OTA. I am not sure i am right or not?

3, slew rate simulation.
how to do the slew rate simulation for SHA?

4, how to pick up the switch size?
How to optimize the Wp/Wn ratio for the switch to get better performance for SHA? what special simulation need to be done? some thesis says it need to do THD simulation?

5, how to evaluate the performance of SHA?
Just do tran simulation and calculate SNR? What other simulation need to be finished?

Thank you in advance

 

[sutapanaki]

Hello guys, some question about pipeline ADC Front end SHA?

1, what's the capacitor mismatch requirement ?
I found that many thesis say ΔC/C< 1 LSB, why it isn't 0.5 LSB? If the ADC resolution is N, ΔC/C<1/2^(N+1) or 1/2^N?

Are you sure those thesis say this for the THA? I guess you mean the global T/H that is in front the whole ADC, not the MDAC which is performing a S/H function too. If the global T/H has a gain error because of capacitor mismatch, then this is like having a gain error in ADC, which usually is not a problem and if desired can be corrected in digital domain. On the other hand if you have a gain error in the OTA of the MDAC this can be problematic since it can reduce the resolution of the ADC. Suppose for example you have a 10 bit pipeline ADC and each stage resolves effectively 1 bit. The first stage produces at the output of the MDAC an amplified version of the quantization error of the 1st stage sub-ADC. The back-end ADC (ADC made of the next 9 stages) measures this q-error and subtracts it in the digital domain from the digital signal coming out of the 1st stage. If there's a gain error higher than 0.5LSB of the back-end ADC, then you don't compensate the q-error of the 1st stage completely which effectively is a reduction in the resolution. Since the gain error of the 1st stage MDAC is deltaC/C we need
deltaC/C<(1/2)*(1/2^9)=1/2^10 or less than 1LSB of the whole ADC.

2, how to do the AC simulation for the OTA used in SHA?
I know ,for the stability ,we should simulate the loop gain( Af) and phase to verify the PM is enough or not. But the feedback capacitor(Cf) connects the input and output of the OTA. how do i open the loop? why?

I found many thesis just open the Cf and let the Cf to be the OTA loading( of cause , the loading include other's capacitors) , then simulate it. But I think it looks like doing the open loop simulation for OTA. I am not sure i am right or not?

Well, you just break the loop, as is usually done in simulating loop gain - for example using the iprobe in cadence. You just need to put the circuit in the right operating conditions corresponding to the hold phase. I would do it by removing any signal, just leaving the common mode voltages and closing the switches to put the THA in hold mode and saving the operating point. Then use this operating point to run AC analysis (or stb analysis in cadence) to see the loop gain.

3, slew rate simulation.
how to do the slew rate simulation for SHA?

Put the circuit in hold mode and apply a large step at the input and look at the output

4, how to pick up the switch size?
How to optimize the Wp/Wn ratio for the switch to get better performance for SHA? what special simulation need to be done? some thesis says it need to do THD simulation?

Yes, you chose the switches such that you achieve your THD spec

5, how to evaluate the performance of SHA?
Just do tran simulation and calculate SNR? What other simulation need to be finished?

Yes, basically tran simulation is the one that's important to measure SFDR and noise simulations to measure SNR.

 

[flesher]

thank you sutapanaki. You did help me a lot.