How to design self checking testbench...

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sandy2811

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How can design self checking testbench for simple 2 input logic gates .....
 

do you understand what a self checking testbench IS?
 

#2 What's your understanding of a self-checking test bench?

#1 Consider the following
simple 2 input logic gates

If we have A OR B = ?
We can have a conditional statement that says
? = 1 when A = '1' OR B = '1' , but not when they are both '0'.

Therefore you have a comparative check based on what you know it should be vs what your uut is outputting.
You can use commands like (vhdl) assert to check and report an output to the console.

For a more robust testbench you really want to be outputting to a text file with test number and test pass/fail state.
 

Self-checking can be done in testbench. You can write a kind of the same behavior code(correct results should be) in testbench and compare the self-checking results in testbench with the data from the code under test. Then, report the comparison results during simulation. You can refer to this as an example testbench: https://www.fpga4student.com/2017/01/verilog-code-for-fifo-memory.html . In this code, I added the self-checking code in the testbench. After writing to the FIFO, I started reading data from FIFO and compare with the data from self-checking code. Then, display the comparison results during simulation.
 
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