[SOLVED] How to design provention of power reverse connection on chip？

[silver_aries]

Hi，everyone.
I am designing a chip based on typical N-well cmos process.I need to design a circuit to provent the chip damage when the power and ground reverse connection.I have read several papers about this topic.But most of them are based on PCB level.Just like set a diode connection in sieries at the VDD PAD,and so on.
Here are my questions:
1、My design don't need too much current.Can I integrate this diode into my chip?If yes,How to design the ESD protection to VDD?
2、Are there any other ways to realize that?

Thanks for helping.

 

[erikl]

If your I/O Lib has the std. ESD protection:

... you could use an input or an I/O pad for your VDD input, if your VDD supply is externally current limited. The anti-parallel diodes of T1 & T2 of the output drivers (corresponding to D1 & D2 of the pure input pad) usually can stand at least 10mA, high current I/O pads about the same current as they can deliver in the output case.

If your external VDD supply isn't limited to such a current, you could perhaps integrate a small pre-resistance - if you can stand the voltage drop (additionally to the diode voltage drop) in the normal function.

 

[silver_aries]

Thanks a lot,erikl.
In my system,there is no place for an external resistor to be set on PCB.I think the second way you provide is a better one than diode.It still will effect the ESD to VDD,but much better than a reversed PN junction of a diode.
Thank you again.You helped me...