How to design PFD in Charge Pump PLL?

[sandip_micro]

Hello friends
I want to ask whats the design procedure of Phase Frequenct Detector Block?
In PFD block we saw 2 D Flip Flops and one AND gate.
Input signals are: REf and fedback and RESET
Output singals are : UP and DN
If the VCO Freq=200 MHZ
Input Freq Range=3 MHZ ~800 MHz

 

[amarnath]

just refer to the johansson pfd since your frequency range is very high. i mean that for the pdf to operate properly at a high frequency the delay through pfd must be less. you can refer to johansson's paper in JSSC


amarnath

 

[sandip_micro]

Heel Amaranath
I want to know the general Design Procedure of PFD Block?
May be i/p freq=100MHz
Then how to start?
Do u have any PDF which explains the design of PFD block?

 

[amarnath]

the pfd is just two d flip flops and a nand gate to reset both of them, size the transistors accordingly. Also do simulations do find out the width of the dead zone and then set the reset path delay slightly greater than the dead zone width.


amarnath