please,i have a problem with a multiplexer 12 input and 9 output
in cypress show this message:
Error: Logic equation has too many product terms on signal sal(8).
Error: Logic equation has too many product terms on signal sal(6).
Error: Logic equation has too many product terms on signal sal(5).
Error: Logic equation has too many product terms on signal sal(4).
Error: Logic equation has too many product terms on signal sal(3).
Error: Logic equation has too many product terms on signal sal(2).
Error: Logic equation has too many product terms on signal sal(1).
Error: Logic equation has too many product terms on signal sal(0).
how i can design this multiplexer in vhdl?
is possibble modify the number product terms?
Hi friend ..
It seems that you have a mapping problem You don't say in the message what type of device you are using but i bet is a CPLD .. Because people that deal with VHDL design for CPLD goes thtough this type of problems .
It seems that you have a piece of vhdl code that systhetizes to a logical statement that implies more than 8 ( depending of the device) Pterms
and This device you are using can't handle more than those 8 (depending of the device in 22v10 is 10 ) i mentioned .
First are you shure that you still have room in the device ..i mean be shure that there are still at least one CELL avalaible .
Otherwise is imposible .. One way to find out is to comment out some of the terms that give you trouble and and compile and GENERATE A REPORT to se cell USAGE ..
If there are cells avalaible well i seems that the sinthetizer that you are using is not very good .. In that case .. create a intermediate term grouping all the signal that didn't fit and plug in the vhdl code this intermediate new term in the original equation ot vhdl statement ..
When dealing with low count CPLD is better to do it using some sort of assambler .CPUL ,PALASM ,ABEL etc .
I took your code and tried to implement in GAL22V10. Impossible, the number of functions you want to implement is to big. It fits in a 128MC device but uses only 21 pins.
Do you realize what you want to do. This is actually a ROM table (input is address, output is data), so I suggest you implement this in a EPROM, or Flash device. OF course you'll need to think this over.
Hi,
I tried to spread the design over 4 GAL22V10, but it didn't work.
However as stated above, you can implement in a medium size CPLD, or use a ROM table and implement in FPGA (what a waste of logic).
I rather suggest using an (E(E))PROM.