How to design last stage of pipelined ADC?

[noiseless]

Because the pipelined ADC last stage cannot be digital corrected, it should be using special method to deal with? Is there anyone knowing how to do that? In the Berkeley Abo's thesis, he did not mention that? Or there is not necessary to do that?

 

[ezt]

Re: design pipelined ADC

Hi.
As you know, error and noise of this last stage will be divided by the whole gain of previous stages to have the input-referred error or noise. Hence, its design would be very relax. Conventionally we assume that this stage contains no error at all. But if this assumption does not hold true, there would be an error in LSB of the final output number and total SNDR won't be degraded dramatically. This is the main reason that nobody talks about the methodology of last stage design.

Regards,
EZT

 

[noiseless]

Re: design pipelined ADC

Ezt,

Thanks. However, if the last bit is not corrected, there will be DNL larger than 1bit. How is the industrial people think about that?

Appreciate

 

[noiseless]

design pipelined ADC

Just put it to the top in order to attract more attention.

 

[talama]

Re: design pipelined ADC

Hi
I want to transmit data from ADXL202 to PC, I can't understand ADC of AVR, So I want to help this problem

 

[schwang1970]

Re: design pipelined ADC

just sue simple flash adc, last stage accuracy is degraded. First stage is most important.

 

[carlyou]

design pipelined ADC

ezt, if I want to do a 10bit, 100Mbps pipeline ADC system design, on system level, how to begin and which parameters should be taken into consideration?
carl