Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] How to design decade up down counter ?

Status
Not open for further replies.

yujeong

Newbie level 5
Newbie level 5
Joined
May 29, 2024
Messages
8
Helped
0
Reputation
0
Reaction score
1
Trophy points
3
Activity points
56
Hello, I would like to create an up-down counter that can count from 0 to 9 using a chip like jk flip-flop. No matter how hard I try, I can only create counters from 0 to 15. Please if anyone knows please help I would appreciate it.
 
Solution
Hi,

do it step by step:
* build an UP counter 0..15
* then build an UP counter 0..9

* Then build a DOWN counter 15..0
* then build a DOWN counter 9 ... 0

* then combine both 0..9 counters

Klaus
First of all thank you for your kindness. I sadly don't know much about this subject. But I have to make this chip and submit it. The way you said it would be difficult for me to make it myself...Honestly, I would like to find out the method and principles of making it, even if it means buying it with money. The task is too difficult compared to what I learned:(
Hi,

No one will write code for free.

And if you need help ... you need to show what you have done so far. .. and tell what you expect .. and tell what did not work like expected.

***
The task is rather clear ... it should count up 0 ... 9 and after 9 it should start with 0. And 0 is rather simple, since it equals the "kill" state of a JK FlipFlop.

Klaus
 

Hi,

No one will write code for free.

And if you need help ... you need to show what you have done so far. .. and tell what you expect .. and tell what did not work like expected.

***
The task is rather clear ... it should count up 0 ... 9 and after 9 it should start with 0. And 0 is rather simple, since it equals the "kill" state of a JK FlipFlop.

Klaus
First of all, thank you for your reply. It's my first time using this site. Please understand that I may make mistakes due to lack of knowledge. I built a circuit with the help of a friend from school, but it was so complex that it was impossible to make and solder. So I decided to create a counter by changing little the file attached below.

1716987280789.png
 

This counter is 0123456789123... In this way, 0 comes out only at the beginning and doesn't come out after that. What is the problem? Please, can anyone tell me, I would appreciate it.

1716998957758.png
 

Just search “decade counter” on the internet. You’ll find a MUCH simpler solution than what you posted
I already looked it up on the internet, but I can't find an up-down counter from 0 to 9.
 

74LS568 is performing the intended function. You can copy datasheet logic diagram or design the logic by standard design methods, e.g. Karnaugh map.

Screenshot_20240529_190748_Dropbox.jpg
 

Hi,

do it step by step:
* build an UP counter 0..15
* then build an UP counter 0..9

* Then build a DOWN counter 15..0
* then build a DOWN counter 9 ... 0

* then combine both 0..9 counters

Klaus
 

    yujeong

    Points: 2
    Helpful Answer Positive Rating
Have you looked into the old 74xx and CD40xx logic
families? These have decade counters, up/down
counters, maybe even the combo.

If you can't find your pony for free then consider
grafting the feedback logic(s) for the decade onto
the up/down counter design. You may (likely will)
need the carry logic to be modal with the U/D state.

Old TI databooks (for TTL) and RCA (for CD4000)
had high quality schematics for all the guts.
 

    yujeong

    Points: 2
    Helpful Answer Positive Rating
Have you looked into the old 74xx and CD40xx logic
families? These have decade counters, up/down
counters, maybe even the combo.

If you can't find your pony for free then consider
grafting the feedback logic(s) for the decade onto
the up/down counter design. You may (likely will)
need the carry logic to be modal with the U/D state.

Old TI databooks (for TTL) and RCA (for CD4000)
had high quality schematics for all the guts.
Thank you very much for your reply. I shouldn't implement the circuit the same way as the datasheet. Since I have to make it myself, it should be simpler and use less chips.
 

Hi,

do it step by step:
* build an UP counter 0..15
* then build an UP counter 0..9

* Then build a DOWN counter 15..0
* then build a DOWN counter 9 ... 0

* then combine both 0..9 counters

Klaus
First of all thank you for your kindness. I sadly don't know much about this subject. But I have to make this chip and submit it. The way you said it would be difficult for me to make it myself...Honestly, I would like to find out the method and principles of making it, even if it means buying it with money. The task is too difficult compared to what I learned:(
 

Solution
This counter is 0123456789123... In this way, 0 comes out only at the beginning and doesn't come out after that. What is the problem?
The count shall reach 0, then immediately the up-count is enabled and remains there all the time the system counts upward. This requires some kind of memory cell.

It makes a difference whether you take outputs from the Q pins or from the bar-Q pins.

Similarly the count shall reach 9, then immediately the down-count is enabled and remains there all the time the system counts downward.

The memory cell can be an RS flip-flop. It takes some experimentation to find how to change state when the count hits 0 and then when the count hits 9.
 

Thank you so much for your help. Why and on what principle are memory cells needed? I'm sorry I'm not good enough..
The count shall reach 0, then immediately the up-count is enabled and remains there all the time the system counts upward. This requires some kind of memory cell.

It makes a difference whether you take outputs from the Q pins or from the bar-Q pins.

Similarly the count shall reach 9, then immediately the down-count is enabled and remains there all the time the system counts downward.

The memory cell can be an RS flip-flop. It takes some experimentation to find how to change state when the count hits 0 and then when the count hits 9.
 

Why and on what principle are memory cells needed?
To enable up-count you need a certain condition (vote) at all 4 bits. And a different condition (vote) to enable the down-count. The required condition goes away with the next count. Once the enable starts in the required direction, you need a memory-cell to hold its state.

Below is a simple memory-cell made from an 'AND' gate using hysteresis. (Not too different from a Schmitt trigger.)
The scope trace shows a 3-bit DAC output (ramp). The upper trace is the enable up-down level, changing state at suitable points in the count.

memory cell (AND gate) provides up-down enable.png
 

    yujeong

    Points: 2
    Helpful Answer Positive Rating
Thank you so much for your help. Why and on what principle are memory cells needed? I'm sorry I'm not good enough..
All counters need memory of 1 FF per bit of binary resolution.

Detecting 0 and 9 is essential to roll-over (0000 and 1001) to the next state for decimal.

To start your design consider all the inputs and outputs you need which may be less than the 74LS568 made to permit cascading larger decimal values than 1 digit.

Then map how to detect each state for counting up or down to see how using the inverted outputs helps.
 

    yujeong

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top