how to design combinational parts of benchmark circuits

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avinashkumar

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hii friends,
This is code i have written for combinational parts of s27 circuit. i think it is not the exact procedure to write plz help me wheather it is correct or where i am getting wrong.

Code Verilog - [expand]
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module s27(G0,G1,G17,G2,G3,G5,G6,G7,G13,G10,G11);
input G0,G1,G2,G3,G6,G5,G7;
output G17,G13,G10,G11;
wire G14,G8,G15,G12,G16,G9;
 not NOT_0(G14,G0);
  not NOT_1(G17,G11);
  and AND2_0(G8,G14,G6);
  or OR2_0(G15,G8,G12);
  or OR2_1(G16,G3,G8);
  nor NOR2_0(G10,G14,G11);
  nor NOR2_1(G11,G5,G9);
  nor NOR2_2(G12,G1,G7);
  nor NOR2_3(G13,G2,G12);
  nand NAND2_1(G9,G16,G15);
 endmodule
 
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Please don't write code at this level. this is called structural verilog and it is essentially the same as putting a schematic together. This type of effort has no place in today's EDA industry. You should be writing RTL.
For the specific ISCAS benchmarks, you can google and download them. No one is writing these anymore, makes no sense.
 
Thanks for your reply , iam using this for atpg. So I have written in structural modelling.
 

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